The present invention relates to solid-state imaging apparatus, and more particularly relates to the solid-state imaging apparatus using an amplified solid-state imaging device having an amplification function within its imaging region.
In recent years, CMOS (Complementary Metal Oxide Semiconductor) type imaging devices (image sensor) are drawing attention and are practically used as solid-state imaging device. The CMOS imaging devices are capable of being driven by a single power supply when compared to CCD (Charge Coupled Device) type imaging devices. Further, while CCD image sensors require an exclusive process, CMOS image sensors can be manufactured through an identical process as other LSI's. The CMOS image sensors can thus be readily made into an SOC (system on chip) so as to be provided with many functions. Furthermore, since the CMOS image sensors have an amplification circuit (amplifier) in each individual pixel to amplify signal electric charge within the pixel, they are less likely to be affected by noise due to the transmission path of signals. Moreover, the signal electric charge of each pixel in the CMOS image sensors may be extracted by means of a selection system so that, in theory, the accumulation time and/or read sequence of signals can be arbitrarily controlled for each pixel.
It is known of the CMOS image sensors that, when a high-luminance light enters, a completely blackened image is formed as if there is not any incidence of light. This phenomenon will be referred to hereinafter as “black sun phenomenon”. The black sun phenomenon will now be described with the operation of a typical CMOS image sensor. FIG. 1 shows a circuit diagram of the CMOS image sensor. A pixel 101 includes: a photodiode PD; a floating diffusion section FD having an electrostatic capacitance of Cfd; a transfer transistor Mtr; a reset transistor Mrs; an amplification transistor Msf; and a select transistor Mse. The pixel 101 is connected through a vertical signal line 102 to a constant current supply 103 and to a CDS (Correlated Double Sampling) circuit 121. The CDS circuit 121 includes: a sample-and-hold transistor Msh; a clamp transistor Mcl; a sample-and-hold capacitor (electrostatic capacitance) Csh; and a clamp capacitor (electrostatic capacitance) Ccl. Further, the CDS circuit 121 is connected to a horizontal signal line 104 through a vertical signal line 102 and a column select transistor Mh. The horizontal signal line 104 is connected to a capacitor (electrostatic capacitance) Ch and to an amplifier 105, and connected through a horizontal signal line reset transistor Mhrs to a horizontal signal line reference voltage Vhrs.
Referring to FIG. 1, those symbols starting with “φ” represent pulse voltages, and those starting with “V” represent voltages at respective locations. Of the pulse voltages, those pulse voltages (transfer pulse φTR, reset pulse φRS, and select pulse φSE) associated with control of the transfer transistor Mtr, reset transistor Mrs, and select transistor Mse within the pixel 101, and the pulse voltage (φH) associated with control of the column select transistor Mh are outputted respectively from a vertical scanning circuit 123 and a horizontal scanning circuit 124 under control of a control signal generation circuit 122. Further, those pulse voltages (sample-and-hold pulse φSH, clamp pulse φCL, and horizontal signal line reset pulse φHRS) associated with control of the sample-and-hold transistor Msh, clamp transistor Mcl, and horizontal signal line reset transistor Mhrs are outputted from the control signal generation circuit 122.
A plurality of the pixels 101 are placed into an array, and electric charges obtained at the photodiode PD are amplified by the amplification transistor Msf in the pixel 101 and are transmitted to the CDS circuit 121. At the CDS circuit 121, the variance of the gate-source voltage (VGS) due to the amplification transistor Msf, and the variance of ktc noise (Vktc) and the feed-through voltage (Vft) due to the reset transistor Mrs that fluctuate from one pixel to another are eliminated by differentiating between the reset signal and the signal of light from each pixel 101. The noise due to the reset transistor Mrs will be referred to hereinafter as Vnoise (=Vktc+Vft).
Shown in FIG. 2 is a timing chart representing the operation of the CMOS image sensor shown in FIG. 1 without an incidence of high-luminance light. At first in the condition where the select pulse φSE, sample-and-hold pulse φSH, and clamp pulse φCL are at High level, the reset pulse φRS is driven to High level. The voltage Vfd at the floating diffusion section FD is thereby set to a power supply voltage Vdd, and an output voltage Vcdsout of the CDS circuit 121 to a clamp reference voltage Vcl. Further, a horizontal signal line voltage Vout is set to a horizontal signal line reference voltage Vhrs by driving the horizontal signal line reset pulse φHRS to High level.
Next when the reset pulse φRS is brought to Low level, the pixel output voltage Vpixout attains a reset voltage Vrst (=Vdd−Vnoise−VGS) as lowered from the power supply voltage Vdd due to the noise Vnoise by the reset transistor Mrs and due to the effect of gate-source voltage VGS at the amplification transistor Msf.
Next at time t1, when the clamp pulse φCL is brought to Low level and the transfer pulse φTR is driven to High level, signal electric charges of light cumulated at the photodiode PD for a predetermined time are transferred to the floating diffusion section FD. The voltage Vfd at the floating diffusion section FD is thereby lowered, and the pixel output voltage Vpixout is also lowered to a pixel light signal voltage Vpixout(sig) in accordance with the signal electric charges. At this time, therefore, the difference ΔVpixout(sig) between the reset voltage Vrst and the pixel section light signal voltage Vpixout(sig) attains ΔVpixout(sig)=Vrst−Vpixout(sig). The CDS circuit output voltage Vcdsout is also lowered to a CDS light signal voltage Vcdsout(sig) in accordance with the signal electric charges. Supposing that Qcl as the amount of electric charges cumulated at the clamp capacitor Ccl at time t1 and Qsh as the amount of electric charges cumulated at the sample-and-hold capacitor Csh, and supposing that Qcl′ as the amount of electric charges cumulated at the clamp capacitor Ccl when the sample-and-hold pulse φSH is brought to Low level at time t2 and Qsh′ as the amount of electric charges cumulated at the sample-and-hold capacitor Csh, the following equations (1), (2) are obtained.
At time t1:Qcl=Ccl(Vrst−Vcl)Qsh=Csh(Vcl−0)  (1)At time t2:Qcl′=Ccl[Vpixout(sig)−Vcdsout(sig)]Qsh′=Csh[Vcdsout(sig)−0]  (2)From the conservation law of the amount of electric charges at time t1, t2, the following equation (3) is obtained.−Qcl+Qsh=−Qcl′+Qsh′Vcl−Vcdsout(sig)=Ccl/(Ccl+Csh)·[Vrst−Vpixout(sig)]ΔVcdsout(sig)=Gcds·ΔVpixout(sig)where: Gcds=Ccl/(Ccl+Csh)  (3)
Here, even with the same amount of light, the pixel output voltage Vpixout is outputted also with having a variance due to the variance of (Vnoise+VGS), i.e. the sum of the noise at the reset transistor Mrs and the gate-source voltage of the amplification transistor Msf of each pixel. By taking difference at the CDS circuit 121 between the pixel light signal voltage Vpixout(sig) and the reset voltage Vrst of each pixel also containing variance components, however, it is possible as shown in the following equation (4) to remove the variance due to the sum (Vnoise+VGS), i.e. the noise at the reset transistor Mrs and the gate-source voltage of the amplification transistor Msf.
                                                                        Vrst                -                                  Vpixout                  ⁡                                      (                    sig                    )                                                              =                            ⁢                                                {                                      Vdd                    -                                          (                                              Vnoise                        +                        VGS                                            )                                                        }                                -                                                                                                      ⁢                              {                                  Vdd                  -                                      (                                          Vnoise                      +                      VGS                      +                                              Δ                        ⁢                                                                                                  ⁢                        Vpixout                        ⁢                                                  (                          sig                          )                                                                                      )                                                  }                                                                                        =                            ⁢                              Δ                ⁢                                                                  ⁢                                  Vpixout                  ⁡                                      (                    sig                    )                                                                                                          (        4        )            
Finally at time t2, by bringing the horizontal signal line reset pulse φHRS to Low level and driving the column select pulse φH to High level, the signal voltage is transmitted to the horizontal signal line 104. Supposing that Qsh as the amount of electric charges cumulated at the sample-and-hold capacitor Csh at time t2 and Qh as the amount of electric charges cumulated at the capacitor Ch connected to the horizontal signal line 104 at the same time, and supposing that Qsh′ as the amount of electric charges cumulated at the sample-and-hold capacitor Csh at time t3 when the horizontal signal line reset pulse φHRS is driven to High level and the column select pulse φH is brought to Low level and Qh′ as the amount of electric charges cumulated at the capacitor Ch connected to the horizontal signal line at the same time, the following equations (5), (6) are obtained.
At time t3:Qsh′=Csh[Vout(sig)−0]Qh′=Ch[Vout(sig)−0]  (5)At time t2:Qsh=Csh[Vcdsout(sig)−0]Qh=Ch[Vhrs−0]  (6)From the conservation law of electric charge at time t2, t3, the following equation (7) is obtained.
                                          Qsh            +            Qh                    =                                    Qsh              ′                        +                          Qh              ′                                      ⁢                                  ⁢                                                                              Vout                  ⁡                                      (                    sig                    )                                                  =                                ⁢                                                                            Csh                      /                                              (                                                  Csh                          +                          Ch                                                )                                                              ·                                          Vcdsout                      ⁡                                              (                        sig                        )                                                                              +                                                                                                                        ⁢                                                      Csh                    /                                          (                                              Csh                        +                        Ch                                            )                                                        ·                  Vhrs                                                                                                        =                                ⁢                                                      Gh                    ·                                          Vcdsout                      ⁡                                              (                        sig                        )                                                                              +                                                            Gh                      ′                                        ·                    Vhrs                                                                                                                          =                                ⁢                                                      Gh                    ⁢                                          {                                                                                                                                  -                              Gcds                                                        ·                            Δ                                                    ⁢                                                                                                          ⁢                                                      Vpixout                            ⁡                                                          (                              sig                              )                                                                                                      +                        Vcl                                            }                                                        +                                                                                                                        ⁢                                                      Gh                    ′                                    ·                  Vhrs                                                                    ⁢                                  ⁢                  therefore          ,                                          ⁢                                                    Gh                ·                Vcl                            +                                                Gh                  ′                                ·                Vhrs                            -              Vout                        =                                          Gh                ·                Gcds                ·                Δ                            ⁢                                                          ⁢                              Vpixout                ⁡                                  (                  sig                  )                                                                    ⁢                                  ⁢                  where          ⁢                      :                          ⁢                                  ⁢                  Gh          =                      Csh            /                          (                              Csh                +                Ch                            )                                      ⁢                                  ⁢                              Gh            ′                    =                      Ch            /                          (                              Csh                +                Ch                            )                                                          (        7        )            Supposing Vcl=Vhrs in this case,Vhrs−Vout(sig)=Gh·ΔVcdsout(sig)ΔVout(sig)=Gh·ΔVcdsout(sig)are attained so that a horizontal signal line light signal voltage ΔVout(sig) corresponding to the signal electric charges generated by the photodiode PD is outputted onto the horizontal signal line 104.
On the basis of the above described circuit operation, the black sun phenomenon will now be described by way of a timing chart of FIG. 3. When a high-luminance light enters into the pixel region, it is possible in some cases that, as shown in FIG. 3, the voltage Vfd at the floating diffusion section FD falls to an allowable minimum value (floating diffusion section minimum voltage Vfdmin) in the period from the bringing of reset pulse φRS to Low level to the driving of the transfer pulse φTR to High level. At this time, the pixel output voltage Vpixout is also lowered to its allowable minimum value (pixel output minimum voltage Vpixoutmin). The reason for this is thought to be for example that an intense light leaks into the floating diffusion section FD so as to generate electric charges not only at the photodiode PD but also at the floating diffusion section FD, or that the electric charges generated at the photodiode PD overflow and are leaked into the floating diffusion section FD.
In this condition, even when the transfer pulse φTR is driven to High level to transmit the signal electric charges of light to the floating diffusion section FD, the voltage Vfd at the floating diffusion section FD is unable to fall beyond the floating diffusion section minimum voltage Vfdmin. For this reason, the pixel output voltage Vpixout also does not fall beyond the pixel output minimum voltage Vpixoutmin so that the difference ΔVpixout(sig) between the reset voltage and the signal voltage is obtained as in the following equation (8) and at the end a horizontal signal line light signal voltage ΔVout(sig)=0 is attained.ΔVpixout(sig)=Vpixoutmin−Vpixoutmin=0  (8)For this reason, a completely darkened image as if without any incidence of light at all results in a pixel region on which the high-luminance light is incident.
Some black sun phenomenon prevention circuits have been proposed to suppress this black sun phenomenon. A description will be given below by way of FIGS. 4 and 5 with respect to a black sun phenomenon prevention circuit disclosed for example in Japanese Patent Application Laid-Open 2000-287131. FIG. 4 shows a circuit diagram to prevent the black sun phenomenon. As shown in FIG. 4, a black sun phenomenon prevention circuit 131 is connected to a vertical signal line 102 to which a pixel 101 is connected. Further, a CDS circuit 121 is connected to the vertical signal line 102. A predetermined reset voltage and a signal voltage of light are then differentiated at the CDS circuit 121, and a difference signal thereof is transmitted to a horizontal signal line 104 through a column select transistor Mh. The black sun phenomenon prevention circuit 131 includes a clip voltage generation transistor MD1 and a prevention circuit actuation transistor MD2. A gate of the clip voltage generation transistor MD1 is connected to a clip reference voltage Vref and a drain to a power supply voltage Vdd, and, on the other hand, a black sun phenomenon prevention circuit actuation pulse φRowD is applied on a gate of the prevention circuit actuation transistor MD2. The black sun phenomenon prevention circuit actuation pulse φRowD in this case is outputted from a control signal generation circuit. Further, a source of the prevention circuit actuation transistor MD2 is connected to the vertical signal line 102.
FIG. 5 shows a timing chart for explaining operation of the black sun phenomenon prevention circuit 131. An operation of the black sun phenomenon prevention circuit 131 will now be described by way of FIG. 5. At first, a reset pulse φRS is driven to High level to set voltage Vfd of a floating diffusion section FD to a power supply voltage Vdd. The black sun phenomenon prevention circuit actuation pulse φRowD is also driven to High level to make effective the black sun phenomenon prevention circuit 131 in advance. The clip reference voltage Vref within the black sun phenomenon prevention circuit 131 is previously set to a voltage lower by Va than the power supply voltage Vdd.
Next, when reset pulse φRS is brought to Low level, the voltage Vfd of the floating diffusion section FD falls to the floating diffusion section minimum voltage Vfdmin due to the effect of a high-luminance light. At this time, since the black sun phenomenon prevention circuit actuation pulse φRowD is at High level, the pixel section output voltage Vpixout does not fall beyond the clip voltage Vc(=Vref−VGSD=Vdd−Va−VGSD) due to the black sun phenomenon prevention circuit 131. Here, VGSD is a gate-source voltage of the clip voltage generation transistor MD1. The black sun phenomenon therefore does not occur even when a high-luminance light is incident, and the difference between the pixel light signal voltage Vpixout(sig) and the clip voltage Vc attainsΔVpixout(sig)′=Vc−Vpixout(sig)(≠0).
As described above, it is possible to avoid the black sun phenomenon by providing the black sun phenomenon prevention circuit 131.